PIC16C63A-04I/SO【PDF 10/184 页】IC MCU OTP 4KX14 PWM 28SOIC

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107

SAM7S Series [DATASHEET]

6175M–ATARM–26-Oct-12

19.2.2

Read Operations

An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added in order to start

access at following address during the second read, thus increasing performance when the processor is running in

Thumb mode (16-bit instruction set). See Figure 19-2, Figure 19-3 and Figure 19-4.

This optimization concerns only Code Fetch and not Data.

The read operations can be performed with or without wait state. Up to 3 wait states can be programmed in the

field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see “MC Flash Mode Register” on page 115).

Defining FWS to be 0 enables the single-cycle access of the embedded Flash.

The Flash memory is accessible through 8-, 16- and 32-bit reads.

As the Flash block size is smaller than the address space reserved for the internal memory area, the embedded

Flash wraps around the address space and appears to be repeated within it.

Figure 19-2. Code Read Optimization in Thumb Mode for FWS = 0

Note:

When FWS is equal to 0, all accesses are performed in a single-cycle access.

Figure 19-3. Code Read Optimization in Thumb Mode for FWS = 1

Note:

When FWS is equal to 1, in case of sequential reads, all the accesses are performed in a single-cycle access (except for the

first one).

Flash Access

Buffer (32 bits)

Master Clock

ARM Request (16-bit)

Code Fetch

Data To ARM

Bytes 0-3

Bytes 4-7

Bytes 0-3

Bytes 0-1

Bytes 2-3

Bytes 4-5

Bytes 6-7

Bytes 8-9

Bytes 10-11

Bytes 12-13

@Byte 0

@Byte 2

@Byte 4

@Byte 6

@Byte 8

@Byte 10

@Byte 12

@Byte 14

@Byte 16

Bytes 14-15

Bytes 4-7

Bytes 8-11

Bytes 12-15

Bytes 16-19

Bytes 12-15

Flash Access

Buffer (32 bits)

Master Clock

ARM Request (16-bit)

Code Fetch

Data To ARM

Bytes 0-3

Bytes 4-7

Bytes 0-3

Bytes 2-3

Bytes 4-5

Bytes 6-7

Bytes 8-9

Bytes 10-11

@Byte 0

@Byte 4

@Byte 6

@Byte 8

@Byte 10

@Byte 12

@Byte 14

Bytes 4-7

Bytes 8-11

Bytes 12-15

1 Wait State Cycle

Bytes 0-1

1 Wait State Cycle

@Byte 2

Bytes 12-13

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